View ISO1H802G_2749002.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

never stop thinking. isoface tm ISO1H802G coreless transformer isolated digital output 8 channel 0.625a high-side switch datasheet , version 2.4, september 2009 power management & drives
ISO1H802G
type on-state resistance package ISO1H802G 200m ? datasheet 3 version 2.4, 2009-09-16 isoface tm ISO1H802G coreless transformer isolated digital output 8 channel 0.625a high-side switch product highlights ? coreless transformer is olated data interface ? galvanic isolation ? 8 high-side output switches 0.625a ? c compatible 8-bit serial peripheral ISO1H802G c (i.e c166) ad0 wr p0.0 p1.x vcc vcc serial interface control unit ct control & protectio n unit cs sclk si dis vcc gndcc gndbb gnd out7 vbb vbb out1 out0 typical application reserved so for daisy chain ? ul508 compliant features ? interface cmos 5v operation compatible ? serial interface ? high common mode transient immunity ? short circuit protection ? maximum current internally limited ? overload protection ? overvoltage protection (including load dump) ? undervoltage shutdown with autorestart and hysteresis ? switching inductive loads ? common output disable pin ? thermal shutdown with restart ? thermal independence of seperate channels ? esd protection ? loss of gndbb and loss of v bb protection ? very low standby current ? reverse battery protection ? rohs compliant typical application ? isolated switch for indust rial applications (plc) ? all types of resistive, inductive and capacitive loads ? c compatible power switch for 24v dc applications ? driver for solenoid, relays and resistive loads description the ISO1H802G is a galvanically isolated 8 bit data interface in pg-dso-36 package that provides 8 fully protected high-side power switches that are able to handle currents up to 625 ma. an serial c compatible interface allows to connect the ic directly to a c system. the input interface is designed to operate with 5v cmos compatible levels. the data transfer from input to output side is realized by the integrated coreless transformer technology.
isoface tm ISO1H802G pin configuration and functionality datasheet 4 version 2.4, 2009-09-16 1 pin configuration and functionality 1.1 pin configuration pin symbol function 1 n.c. not connected 2 vcc positive 5v logic supply 3 dis output disable 4 cs chip select 5 sclk serial clock 6 si serial data input 7 n.c. not connected 8 n.c. not connected 9 n.c. not connected 10 n.c. not connected 11 n.c. not connected 12 n.c. not connected 13 so serial data output 14 reserved - 15 gndcc input logic ground 16 n.c. not connected 17 n.c. not connected 18 n.c. not connected 19 gndbb output driver ground 20 n.c not connected 21 out7 high-side output of channel 7 22 out7 high-side output of channel 7 23 out6 high-side output of channel 6 24 out6 high-side output of channel 6 25 out5 high-side output of channel 5 26 out5 high-side output of channel 5 27 out4 high-side output of channel 4 28 out4 high-side output of channel 4 29 out3 high-side output of channel 3 30 out3 high-side output of channel 3 31 out2 high-side output of channel 2 32 out2 high-side output of channel 2 33 out1 high-side output of channel 1 34 out1 high-side output of channel 1 35 out0 high-side output of channel 0 36 out0 high-side output of channel 0 tab vbb positive driver power supply voltage vcc n.c. 1 dis figure 1 power so-36 (430mil) .
datasheet 5 version 2.4, 2009-09-16 isoface tm ISO1H802G pin configuration and functionality 1.2 pin functionality vcc (positive 5v logic supply) the vcc supplies the input interface that is galvanically isolated from t he output driver stage. the input interface can be supplied with 5v. dis (output disable) the high-side outputs out0...out7 can be immediately switched off by means of the low active pin dis that is an asynchronous signal. the input registers are also reset by the dis signal. the output remains switched off after low-high transient of dis , till new data is written into th e input interface. current sink to gndcc cs (chip select) the system microcontroller selects the ISO1H802G by means of the low active pin cs to activate the interface. current source to vcc sclk (serial shift clock) sclk (serial clock) is used to synchronize the data transfer between the master and the ISO1H802G. data present at the si pin are latched on the rising edge of the serial clock input, while data at the so pin is updated after the fa lling edge of sclk in serial mode. current source to vcc si (serial data input) this pin is used to transfer data into the device. data is latched on the rising edge of the serial clock. current sink to gndcc so (serial data output) this pin is used when the se rial interface is activated. so can be connected to a serial input of a further ic to built a daisy-chain configurati on. it is only actvated if cs is in low state, otherwise this output is in high impedance state. gndcc (ground for vcc domain) this pin acts as the ground reference for the input interface that is supplied by vcc. gndbb (output driver ground domain) this pin acts as the ground reference for the output driver that is supplied by vbb. out0 ... out7 (high side output channel 0 ... 7) the output high side channels are internally connected to vbb and controlled by the corresponding data input. tab (vbb, positive supply for output driver) the heatslug is connected to the positive supply port of the output interface.
datasheet 6 version 2.4, 2009-09-16 isoface tm ISO1H802G blockdiagram 2blockdiagram serial input interface so sclk cs overvoltage protection undervoltage shutdown with res tart voltage source common diagnostic output ct serial to parallel to logic channel 1 - 6 temperature sensor out0 overload protection current limitation limitation of unclamped inductive load logic charge pump level shifter rectifier high-side channel 0 temperature sensor out7 overload protection current limitation limitation of unclamped inductive load logic charge pump level shifter rectifier high-side channel 7 channel 1 ... 6 from temperature sensor channel 1 - 6 to logic channel 1 - 6 vbb logic undervoltage shutdown with restart vbb gndbb vcc gndcc galvanic isolation dis out1 out2 out3 out4 out5 out6 gate protection gate protection ISO1H802G reserved si figure 2 blockdiagram
isoface tm ISO1H802G functional description datasheet 7 version 2.4, 2009-09-16 3 functional description 3.1 introduction the isoface ISO1H802G includes 8 high-side power switches that are controlled by means of the integrated c compatible spi interface. the outputs out0...out7 are controlled by the data of the serial input si. the ic can replace 8 optocouplers and the 8 high-side switches in conventional i/o-applications as a galvanic isolation is implemented by means of the integrated coreless transformer technology. the c compatible interfac es allow a direct connection to the ports of a microcontroller without the need for other components. each of the 8 high-side power switches is protected against short to vbb, overload, overtemperature and against overvoltage by an active zener clamp. the diagnostic logic on the power chip recognizes the overtemperature information of each power transistor. 3.2 power supply the ic contains 2 galvanic isolated voltage domains that are independent from each other. the input interface is supplied at vcc and the output stage is supplied at vbb. the different voltage domains can be switched on at different time . the output stage is only enabled once the input stage enters a stable state. 3.3 output stage each channel contains a high-side vertical power fet that is protected by embed ded protection functions. the continuos current for each channel is 625ma (all channels on). 3.3.1 output stage control each output is independently controlled by an output latch and a common reset line via the pin dis that disables all eight outputs an d reset the latches. serial data input (si) is read on the rising edge of the serial clock sclk. a logic high input data bit turns the respective output channel on, a logic low data bit turns it off. cs must be low whilst shifti ng all the serial data into the device. a low- to-high transition of cs transfers the serial data input bits to the output buffer. 3.3.2 power transistor overvoltage protection each of the eight output stages has its own zener clamp that causes a voltage limitation at the power transistor when solenoid loads are switched off. v on is then clamped to 47v (min.). vz vbb gndbb outx v on vbb figure 3 inductive and overvoltage output clamp (each channel) energy is stored in the load inductance during an inductive load switch-off. e l 12 ? li l 2 = e l gndbb v bb outx e r l r l e load z l vbb e bb e as dx figure 4 inductive load switch-off energy dissipation (each channel) while demagnetizing the load inductance, the energy dissipation in the dmos is e as e bb e l e r ? v on cl () i l t () dt = + = with an approximate solution for r l > 0 ? e as i l l 2r l --------------- - v bb v on cl () + () 1 i l r l v on cl () ------------------------ - + ?? ?? ln = 3.3.3 power transistor overcurrent protection the outputs are provided with a current limitation that enters a repetitive switched mode after an initial peak current has been exceeded. the initial peak short circuit current limit is set to i l(scp) at t j = 125c. during the repetitive mode short circuit current limit is set to i l(scr) . if this operation leads to an overtemperature
datasheet 8 version 2.4, 2009-09-16 isoface tm ISO1H802G functional description condition, a second protection level (t j > 135c) will change the output into a low duty cycle pwm (selective thermal shutdown with restart) to prevent critical chip temperatures. in vout t j t t t figure 5 overtemperatu re detection the following figures show the timing for a turn on into short circuit and a short circ uit in on-state. heating up of the chip may require several milliseconds, depending on external conditions. in vout i l t t t output short to gnd i l(scp) i l(scr) figure 6 turn on into short circuit, shut down by overtemperature, restart by cooling in vout i l t t t output short to gnd i l(scp) i l(scr) normal operation figure 7 short circuit in on-state, shut down down by overtemperature, restart by cooling 3.4 reserved 3.5 serial interface the ISO1H802G contains a serial interface that can be directly controlled by the microcontroller output ports. 3.5.1 spi signal description cs - chip select. the syst em microcontroller selects the ISO1H802G by means of the cs pin. whenever the pin is in a logic low state, data can be transferred from the c. cs high to low transition: ?serial input data can be clocked in from then on ?so changes from high impe ndance state to logic high or low state corresponding to the so bit-state cs low to high transition: ?transfer of si bits from shift register into output buffers, if number of clock signals was an integer multiple of 8 ?so changes from the so bit-state to high impendance state to avoid any false clocking the serial input pin sclk should be logic high state during high-to-low transition of cs . when cs is in a logic high state, any signals at the sclk and si pins are ignored and so is forced into a high impedance state. the integrated modulo counter that counts the number of cl ocks avoids the take over of invalid commands caused by a spike on the clock line or wrong number of clock cycles. a command is only taken over if after the low-to-high transition of the cs signal the number of counted clock cycles is an integer multiple of 8. sclk - serial clock. the system clock pin clocks the internal shift register of the ISO1H802G. the serial input (si) accepts data into the input shift register on the rising edge of sclk while the serial output (so) shifts the output information out of the shift register on the falling edge of the serial clock. it is essential that the sclk pin is in a logic high state whenever chip select
datasheet 9 version 2.4, 2009-09-16 isoface tm ISO1H802G functional description cs makes any transition. the number of clock pulses will be counted during a chip se lect cycle. the received data will only be accepted, if exactly an integer multiple of 8 clock pulses were counted during cs is active. si - serial input. serial data bits are shifted in at this pin, the most significant bit first. si information is read in on the rising edge of the sclk. input data is latched in the shift register and then transferred to the control buffer of the output stages. so - serial output. so is in a high impedance state until the cs pin goes to a logic low state. the data of the internal shift register are shifted out serially at this pin. the most significant bit will app ear at first. the further bits will appear following th e falling edge of sclk. 3.5.2 spi bus concepts 3.5.2.1 independent individual control each ic with a spi is controlled individually and independently by an spi master, as in a directional point-to-point communication.the port requirements for this topology are the greatest, because for each controlled ic an individual spi at the c is needed (sclk, cs , si). all ics can be addressed simultaneously with the full spi bandwidth. spi - interface ic1 output lines spi - interface icn output lines c spi 1 spi n sclk cs si sclk cs si clk tx a1 tx a2 clk tx n1 tx n2 number of addressed ics = n number of necessary control and data ports = 3 n individual ics are addressed by the chip select so so figure 8 individual independent control of each ic with spi 3.5.2.2 daisy-chain configuration the connection of different ics and a c as shown in fig. 11 is called a daisy-ch ain. for this type of bus- topology only one spi interf ace of the c for two or more ics is needed. all ics share the same clock and chip select port of the spi master. that is all ics are active and addressed simult aneously. the data out of the c is connected to the si of the first ic in the line. each so of an ic is connected to the si of the next ic in the line. spi - interface output lines spi - interface output lines c spi 1 clk tx a1 tx a2 number of addressed ics = n number of necessary control and data ports = 3 all ics are addressed by the common chip select icn ic1 sclk cs si sclk cs so si figure 9 spi bus all ics in a ?daisy chain? configuration the c feeds to data bits into the si of ic1 (first ic in the chain). the bits coming from the so of ic1 are directly shifted into the si of the next ic. as long as the chip select is inactive (logi c high) all the ic spis ignore the clock (sclk) and input signals (si) and all outputs (so) are in tristate. as long as the chip select is active the spi register works as a simple shift register. with each clock signal one input is shifted into the spi register (si), each bit in the shift register moves one position further within the register, and the last bit in the spi shift register is shifted out of so. this continuous as long as the chip select is active (logic low) and clock signals are applied. the data is then only taken over to the output buffers of each ic when the cs signal changes to high from low and recognized as valid data by the internal modulo counter.
datasheet 10 version 2.4, 2009-09-16 isoface tm ISO1H802G functional description 3.6 transmission failure detection there is a failure detection unit integrated to ensure also a stable functionality during the integrated coreless transformer transmission. this unit decides wether the transmitted data is valid or not. if four times serial data coming from the internal registers is not accepted the output stages are switched off until the next valid data is received.
isoface tm ISO1H802G functional description datasheet 11 version 2.4, 2009-09-16 3.7 serial interface timing cs sclk si n+7 n+6 n+5 n+4 n+3 n+2 n+1 n n-1 n-2 n-3 n-4 n-5 n-6 n-7 so n chip select active figure 10 serial interface cs sclk si t css t csh t csd t su t hd
datasheet 12 version 2.4, 2009-09-16 isoface tm ISO1H802G electrical characteristics 4 electrical characteristics note: all voltages at pins 2to 14 are measured with respec t to ground gndcc (pin 15). all voltages at pin 20 to pin 36 and tab are measured with respect to ground gn dbb (pin 19). the voltage levels are valid if other ratings are not violated. the two voltage domains v cc ,gnd cc and v bb ,gnd bb are internally galvanic isolated. 4.1 absolute maximum ratings note: absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. for the same reason make sure, that any capac itor that will be connected to pin 2 (vcc) and tab (vbb) is discharged before assembling the application circuit. supply voltages higher than v bb(az) require an external current limit for the gndbb pin, e.g. with a 15 ? resistor in gndbb connection. operating at absolute maximum ratings can lead to a reduced lifetime. parameter at t j = -40 ... 135c, unless otherwise specified symbol limit values unit min. max. supply voltage input interface (vcc) v cc -0.5 6.5 v supply voltage output interface (vbb) v bb 1) defined by p tot -1 1) 45 continuous voltage at pin si v dx -0.5 6.5 continuous voltage at pin cs v cs -0.5 6.5 continuous voltage at pin sclk v wr -0.5 6.5 continuous voltage at pin dis v dis -0.5 6.5 continuous voltage at pin so v dx -0.5 6.5 continuous voltage at reserved pin v reserved -0.5 6.5 load current (short-circuit current) i l --- self limited a reverse current through gndbb 1) i gndbb -1.6 --- operating temperature t j -25 internal limited c storage temperature t stg -50 150 power dissipation 2) device on 50mm*50mm*1.5mm epoxy pcb fr4 with 6cm2 (one layer, 70m thick) copper area for drain connection. pcb is vertical without blown air. 2) p tot --- 3.3 w inductive load switch-off energy dissipation 3) not subject to production test, specified by design 3) single pulse, t j = 125c, i l = 0.625a one channel active all channel simultaneously active (each channel) e as --- 10 1 j load dump protection 3) v loaddump 4) v loaddump is setup without the dut connected to the generator per iso7637-1 and din40839 4) =v a + v s v in = low or high t d = 400ms, r i = 2w, r l = 27w, v a = 13.5v t d = 350ms, r i = 2w, r l = 57w, v a = 27v v loaddump --- --- 90 117 v electrostatic discharge voltage (human body model) according to jesd22-a114-b v esd 2 kv electrostatic discharge voltage (charge device model) according to esd stm5.3.1 - 1999 v esd 1 kv continuous reverse drain current 1)3) , each channel i s --- 4 a
isoface tm ISO1H802G electrical characteristics datasheet 13 version 2.4, 2009-09-16 4.2 thermal characteristics parameter at t j = -25 ... 125c, v bb =15...30v, v cc = 4.5...5.5v, unless otherwise specified symbol limit values unit test condition min. typ. max. thermal resistance junction - case r thjc --- --- 1.5 k/w thermal resistance @ min. footprint r th(ja) --- --- 50 thermal resistance @ 6cm2 cooling area 1) device on 50mm*50mm*1.5mm epoxy pcb fr4 with 6cm2 (one layer, 70m thick) copper area for drain connection. pcb is vertical without blown air. 1) r th(ja) --- --- 38 4.3 load switching capabi lities and characteristics parameter at t j = -25 ... 125c, v bb =15...30v, v cc = 4.5...5.5v, unless otherwise specified symbol limit values unit test condition min. typ. max. on-state resistance, i l = 0.5a, each channel t j = 25c t j = 125c two parallel channels, t j = 25c: 1) four parallel channels, t j = 25c: 1 r on --- --- 150 270 75 38 200 320 100 50 m ? nominal load current device on pcb 38k/w, t a = 85c, t j < 125c one channel: 1) not subject to production test, specified by design 1) two parallel channels: 1) four parallel channels: 1) i l(nom) 0.7 1.1 2.2 a turn-on time to 90% v 2) the turn-on and turn-off time includes the switching time of the high-side switch and the transmission time via the coreless transformer in normal operating mode. during a failure on the co reless transformer transmission turn-on or turn-off time can increase by up to 50s. out 2) r l = 47 ? , v dx = 0 to 5v t on --- 64 120 s turn-off time to 10% v out 1) r l = 47 ? , v dx = 5 to 0v t off --- 89 170 slew rate on 10 to 30% v out r l = 47 ? , v bb = 15v dv/dt on --- 1 2 v/s slew rate off 70 to 40% v out r l = 47 ? , v bb = 15v -dv/dt off --- 1 2 4.4 operating parameters parameter at t j = -25 ... 125c, v bb =15...30v, v cc = 4.5...5.5v, unless otherwise specified symbol limit values unit test condition min. typ. max. common mode transient immunity 1) dv iso /dt -25 - 25 kv/s dv iso = 500v magnetic field immunity 1) h im 100 a/m iec61000-4-8 voltage domain v bb (output interface) undervoltage shutdown v bb(under) 7 --- 10.5 v undervoltage restart v bb(u_rst) --- --- 11
datasheet 14 version 2.4, 2009-09-16 isoface tm ISO1H802G electrical characteristics 4.5 output protection functions parameter 1) integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as ?out side? normal operating range. protection functions are not designed for continuos repetitive operation. 1) at t j = -25 ... 125c, v bb =15...30v, v cc =4.5...5.5v, unless otherwise specified symbol limit values unit test condition min. typ. max. initial peak short circuit current limit, each channel v bb = 30v, t m = 700s t j = -25c t j = 25c t j = 125c two parallel channels: 3) four parallel channels: 3) i l(scp) --- --- 0.7 --- 1.4 --- 1.9 --- --- a twice the current of one channel four times the current of one channel repetitive short circuit current limit 3) t j = t jt (see timing diagrams) each channel: two parallel channels: 3) four parallel channels: 3 ) i l(scr) --- 1.1 1.1 1.1 --- output clamp (inductive load switch off) at v out = v bb - v on(cl) v on(cl) 47 53 60 v overvoltage protection v bb(az) 47 --- --- thermal overload trip temperature 2) higher operating temperature at normal function for each channel available 3) not subject to production test, specified by design 2) 3) t jt 135 --- --- c thermal hysteresis 3) ? t jt --- 10 --- k 4.6 reserved undervoltage hysteresis ? v bb(under) --- 0.5 --- undervoltage current i bb(uvlo) --- 1 2.5 ma v bb < 7v operating current i gndl --- 10 14 ma all channels on - no load leakage output current (included in i bb(off) ) v dx = low, each channel i l(off) --- 5 30 a voltage domain v cc (input interface) operating voltage v cc 4.5 --- 5.5 v undervoltage shutdown v cc(under) 2.5 --- 2.9 undervoltage restart v cc(u_rst) --- --- 3 undervoltage hysteresis ? v cc(under) --- 0.1 --- undervoltage current i cc(uvlo) --- 1 2 ma v cc < 2.5v operating current i cc(on) --- 4.5 6 ma 1) not subject to production test
isoface tm ISO1H802G electrical characteristics datasheet 15 version 2.4, 2009-09-16 4.7 input interface parameter at t j = -25 ... 125c, v bb =15...30v, v cc = 4.5...5.5v, unless otherwise specified symbol limit values unit test condition min. typ. max. input low state voltage (si, dis , cs , sclk) v il -0.3 --- 0.3 x v cc v input high state voltage (si, dis , cs , sclk) v ih 0.7 x v cc --- v cc + 0.3 input voltage hysteresis (si, dis , cs , sclk) v ihys 100 mv output low state voltage (so) v ol -0.3 --- 0.25 x v cc v c l < 50pf, r l > 10k ? output high state voltage (so) v oh 0.75 x v cc --- v cc + 0.3 input pull down current (si , dis ) i idown 100 a input pull up current ( cs , sclk) -i iup 100 output disable time (transition dis to logic low) 1)2) 1) the time includes the turn-on/off time of the high-side switch and the transmission time via the coreless transformer. 2) if pin dis is set to low the outputs are set to low; after dis set to high a new write cycle is nec essary to set the output again. normal operation turn-off time to 10% v out r l = 47 ? t dis --- 85 170 s output disable time (transition dis to logic low) 3) the parameter is not subject to production test - verified by design/characterization 1)2)3) disturbed operation turn-off time to 10% v out r l = 47 ? t dis --- --- 230
datasheet 16 version 2.4, 2009-09-16 isoface tm ISO1H802G electrical characteristics 4.8 spi timing parameter at t j = -25 ... 125c, v bb =15...30v, v cc = 4.5...5.5v, unless otherwise specified symbol limit values unit test condition min. typ. max. serial clock frequency f sclk dc --- 20 mhz serial clock period (1/fclk) t p(slck) 50 --- --- ns cs setup time (falling edge of cs to falling edge of sclk) t css 5 --- --- cs hold time (rising edge of sclk to rising edge of cs ) t csh 10 --- --- cs disable time ( cs high time between two accesses) t csd 10 --- --- data setup time (required time si to rising edge of sclk) t su 6 --- --- data hold time (falling edge of sclk to si) t hd 6 --- --- so output valid time cl = 50pf t valid --- --- 20 so output disable time t sodis 20 4.9 reverse voltage parameter at t j = -25 ... 125c, v bb =15...30v, v cc = 4.5...5.5v, unless otherwise specified symbol limit values unit test condition min. typ. max. reverse voltage 1) defined by p tot 2) not subject to production test, specified by design 1)2) r gnd = 0 ? r gnd = 150 ? -v bb --- --- --- --- 1 45 v diode forward on voltage if = 1.25a, v dx = low, each channel -v on --- --- 1.2
isoface tm ISO1H802G electrical characteristics datasheet 17 version 2.4, 2009-09-16 4.10 isolation and safety-related specification parameter value unit conditions rated dielectric isolation voltage v iso 500 v ac 1 - minute duration 1) not subject to production test, verified by charac terization; production test with 1100v, 100ms duration 1) short term temporary overvoltage 1250 v 5s acc. din en60664-1 1) minimum external air gap (clearance) 2.6 mm shortest distance through air. minimum external tracking (creepage) 2.6 mm shortest distance path along body. minimum internal gap 0.01 mm insulation distance through insulation approvals: ul508, csa c22.2 no.14 certificate nu mber: 20090514-e329661 4.11 reliability for qualification report please contact your local infineon technologies office!
datasheet 18 version 2.4, 2009-09-16 isoface tm ISO1H802G package outlines 5 package outlines bottom view does not include plastic or metal protrusion of 0.15 max. per side 1 18 0.25 0.1 1.1 36 +0.13 0.25 36x 19 m (heatslug) 15.74 0.65 0.1 c ab 19 c 3.25 3.5 max. +0.1 0 0.1 0.1 36 2.8 b 11 0.15 1) 1.3 5? 0.25 3? -0.02 +0.07 6.3 14.2 (mold) 0.3 b 0.15 0.25 heatslug 0.95 heatslug 0.1 5.9 3.2 (metal) 0.1 (metal) 13.7 (metal) 10 1 -0.2 index marking (mold) 15.9 1) 0.1 a 1 x 45? 1) gps09181_1 pg-dso-36 (plastic dual small outline package) figure 13 pg-dso-36
datasheet 19 version 2.4, 2009-09-16 isoface tm ISO1H802G package outlines
datasheet 20 version 2.4, 2009-09-16 isoface tm ISO1H802G package outlines
isoface tm ISO1H802G package outlines datasheet 21 version 2.4, 2009-09-16
published by infineon technologies ag www.infineon.com qualit?t hat f?r uns eine umfassende bedeutung. wir wollen allen ihren anspr?chen in der bestm?glichen weise gerecht werden. es geht uns also nicht nur um die produktqualit?t ? unsere anstr engungen gelten gleicherma?n der li eferqualit?t und logistik, dem service und support sowie allen sonstigen beratungs- und betreuungsleistungen. dazu geh?rt eine bestimmte geisteshaltung unserer mitarbeiter. total quality im de nken und handeln gegen?ber kollegen, lieferanten und ihnen, unserem kunden. unsere leitlinie ist jede aufgabe mit ?ull fehlern?zu l?sen ?in offener sichtweise auch ?ber den eigenen arbeitsplatz hinaus ?und uns st?ndig zu verbessern. unternehmensweit orientieren wir uns dabei auch an ?op?(time optimized processes), um ihnen durch gr??re schnelligkeit d en entscheidenden wettbewerbsvorsprung zu verschaffen. geben sie uns di e chance, hohe leistung durch umfassende qualit?t zu beweisen. wir werden sie ?berzeugen. quality takes on an all encompassing significance at se miconductor group. for us it means living up to each and every one of your demands in the best possible way. so we are not only concerned with product quality. we direct our efforts equ ally at quality of supply and logistics, service and support, as well as al l the other ways in which we advise and attend to you. part of this is the very special attitude of our staff. total qual ity in thought and deed, towards co-w orkers, suppliers and you, our customer . our guideline is ?o everything with zero defects? in an open manner that is demonstrated beyond your immediate workplace, and to constantly improve. throughout the corporation we also think in terms of time optimized processes (top), gr eater speed on our part to give you that decisive competitive edge. give us the chance to prove the best of performance through the best of quality ?you will be convinced. total quality management

▲Up To Search▲

Price & Availability of ISO1H802G

	To Download ISO1H802G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .